The present invention relates to interfaces for electronic communications systems and particularly to a packet switching system which enables a data matrix to be converted to a serial bit stream which is transmitted over a single data link such as twisted pair and thereafter reconstituted in real time.
Data transmission from a central data source to one or more utilization circuits, such as a display, generally takes one of two forms. In the first form, the data is transmitted to the utilization circuit in parallel and in real time. While such a system is desirable in many applications, the method requires a multiplicity of conductors, drivers, and other components and is limited as to the number of loads and distance between data source and utilization circuit. Consequently, it is a relatively high cost system which is inherently low in reliability.
The second form of data transmission is serial but not in real time. This method requires extensive hardware to receive, store, and reformat the data. Such non-real time serial data transmission will necessarily be of limited speed as well.
The present invention overcomes the above disadvantages and provides a novel method of serial data transmission in real time. The method and apparatus has particular application in the field of multiplex displays. Multiplex displays commonly use two latches, one for column select and one for row select. In a conventional multiplex display, first the column latch is loaded and then the first row latch is enabled thus activating the first row of lights in the display. Thereafter, the row latch is disabled, new data is loaded into the column latch, and the next row latch is enabled. This process is repeated continuously and produces a stationary or moving image on the display.
By contrast, the present invention generates a series of data words each containing the data byte from one cell in a matrix array desired to be transmitted to a remote utilization circuit. Following each set of data words representative of the sequentially sampled data in one dimension, a final address word is formed which does not contain data but rather contains the address of, for example, a row from which all of the immediately preceding data bytes were obtained. A flag or steering bit in each word indicates to the decoding or receiving circuitry whether the transmitted word constitutes a data word from the matrix or an address word.
At the remote utilization circuit, the serial string of data is first synchronized by sensing, e.g., an always low start bit. Thereafter, the data address byte of each received word is shifted into a shift register equal in length to the length of the data and address byte. The data byte and address byte have the same number of bits. Hence, if the data byte has eight bits, the shift register would also be eight storage locations. Once the eight address or data bits have been shifted into the shift register, further shifting into the shift register is disabled until the next start bit of the next word is sensed at which time the data will be shifted out of the shift register as new data is shifted in. Therefore, when the shift register is disabled, one and only one complete data or address byte will appear in the shift register. Immediately after data or address bits are shifted into the shift register, logic circuitry looks at the steering bit and determines whether the data in the shift register constituted a data byte or an address byte. If, in fact, the information is an address byte, then the data in the shift register may be appropriately sampled and decoded to obtain the address information. That information may then be transferred to a suitable utilization circuit. The previously received series of data bytes could also be transferred to the utilization circuit to be gated to the appropriate memory or display row indicated by the address information. Thus, it will be appreciated that the transmission is real time and does not require substantial memory or decoding logic.